A buck converter takes a higher DC voltage and steps it down efficiently by switching a transistor on and off very fast. On a datasheet it looks clean: 12 V in, 5 V out. On an oscilloscope the output is never a flat line — it carries a small, periodic wobble called ripple. Ripple is not a defect; it is an unavoidable consequence of switching. The engineer's job is not to eliminate it but to size the inductor and output capacitor so the ripple stays within budget.
This article explains where buck-converter ripple comes from, works the numbers for a realistic design, and explains why the capacitor's parasitic resistance often matters more than its capacitance.
Why this calculation matters
Ripple is a specification, not an afterthought. Digital loads, sensitive analog circuits, and RF sections all have a maximum supply-ripple they tolerate. Exceed it and you get bit errors, elevated noise floors, or audible whine. The two components that set the ripple — the inductor and the output capacitor — are also among the largest and most expensive parts in the converter.
Oversize them and you waste board area and cost. Undersize them and the converter fails its noise spec, or the inductor saturates and the design becomes unreliable. Calculating ripple up front is how you land in between: meeting the spec without paying for margin you do not need.
The core formulas
Ripple analysis starts with the duty cycle, the fraction of each switching period the transistor is on. For an ideal buck converter:
D = Vout / Vin
While the switch is off, the output voltage drives current down through the inductor. That produces a triangular inductor ripple current:
delta_IL = Vout * (1 - D) / (L * fsw)
where L is the inductance and fsw the switching frequency. A larger inductor or a higher switching frequency both shrink the current ripple.
That triangular current flows into the output capacitor, and it produces output voltage ripple through two separate mechanisms.
The first is the capacitance itself charging and discharging:
delta_Vcap = delta_IL / (8 * C * fsw)
The second, often larger, is the ripple current flowing through the capacitor's equivalent series resistance (ESR) — a real, parasitic resistance inside every capacitor:
delta_Vesr = delta_IL * ESR
The total output ripple is a combination of these two. Which one dominates is the central design insight.
A worked example
Design point: Vin = 12 V, Vout = 5 V, switching frequency fsw = 500 kHz, inductor L = 10 µH, output capacitor C = 47 µF with an ESR of 20 mOhm.
Step 1 — duty cycle.
D = 5 / 12 = 0.417
Step 2 — inductor ripple current.
delta_IL = 5 x (1 - 0.417) / (10e-6 x 500e3)
delta_IL = 5 x 0.583 / 5.0 = 0.583 A
The inductor current swings about 0.58 A peak-to-peak around its DC average.
Step 3 — capacitive ripple component.
delta_Vcap = 0.583 / (8 x 47e-6 x 500e3) = 0.583 / 188 = 3.1 mV
Step 4 — ESR ripple component.
delta_Vesr = 0.583 x 0.020 = 11.7 mV
Here is the punchline. The capacitance contributes about 3 mV; the ESR contributes nearly 12 mV — almost four times as much. For this design — a 47 uF capacitor with 20 mOhm of ESR, typical of an electrolytic or polymer part — the output ripple is dominated by ESR, not by capacitance. Adding more microfarads of the same capacitor type barely helps. To cut the ripple you need lower ESR: a better dielectric, or several capacitors in parallel so their ESRs divide. With a bank of low-ESR ceramics the balance can tip back, and the capacitive term sets the ripple instead.
Common mistakes
Choosing a capacitor by capacitance alone. As the example shows, ESR often sets the ripple. A 47 µF low-ESR ceramic can outperform a 470 µF electrolytic with high ESR. Read the ESR spec, not just the microfarad value.
Ignoring inductor saturation. The peak inductor current is the DC load current plus half the ripple. If that peak exceeds the inductor's saturation rating, the inductance collapses, ripple explodes, and the converter can fail. Always check the peak, not the average.
Forgetting the discontinuous-conduction mode. The ripple formulas above assume continuous conduction — the inductor current never reaches zero. At light load the converter can enter discontinuous mode, where the behaviour and the equations change.
Assuming higher frequency is free. Raising fsw shrinks ripple and shrinks the magnetics, which is tempting. But switching losses rise with frequency, hurting efficiency and adding heat. It is a genuine trade-off, not a free lunch.
Try the interactive NovaSolver calculator
Ripple design is a balancing act between L, C, ESR, and fsw, and it is far easier to feel when the numbers move together. The buck converter ripple calculator on NovaSolver computes duty cycle, inductor ripple current, and both ripple components — so you can see immediately whether your design is capacitance-limited or ESR-limited.
Related calculators
- Boost converter duty cycle — the step-up sibling topology and its operating point.
- PWM control — the pulse-width modulation that sets the duty cycle in the first place.
- Inductor RL behaviour — how current builds and decays in an inductor, the mechanism behind the ripple.
The full set is in the power electronics tools hub.
Closing note
Buck-converter ripple is a small calculation that decides whether a power supply quietly does its job or pollutes everything downstream. The chain of logic is short: duty cycle sets the operating point, the inductor and switching frequency set the ripple current, and that current turns into output ripple through both capacitance and ESR. The lesson most beginners miss is to look past the microfarad rating: depending on the capacitor technology, ESR often sets the ripple. Size L for an acceptable ripple current, check the saturation peak, and choose the output capacitor for low ESR — and your output will look like the flat line the datasheet promised.
